CALL
FOR PARTICIPATION |
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Overview |
THEME
Process Variations + Systematic Defects: Can DBT Help?
As we push deeper into nanometer technologies, systematic defects are outstretching random defects as the dominant yield limiter and are presenting unique challenges to the yield enhancement community. New methodologies are required to detect, monitor, and resolve systematic defect mechanisms at the 90nm technology node and below. As mainstream silicon manufacturing processes scale to and beyond the 65-nm node, we also find the mean and variance of process variations increasing. Fallout caused by systematic defects is obfuscated by process variations, making them more difficult to distinguish using traditional testing methods. This year's workshop is charged with determining whether defect-based test is better positioned to provide information regarding root cause, and whether such methods can help with the identification and isolation of systematic defects.
The IEEE International Workshop on Current and Defect Based Testing (DBT 2007) is aimed at addressing these issues and others related to this year’s theme “Process Variations + Systematic Defects: Can DBT Help?” Paper presentations on topics related to the workshop’s theme and to those given below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.
The workshop includes (but is not limited to) the following topics:
- Test Data Analysis
- Transition and Delay Testing
- IDDQ and IDDT Testing
- Low voltage Testing
- Noise and Cross-talk Testing
- Defect Coverage & Metrics
- Economics of Defect Based Testing
- Outlier Identification
- Data-Mining approaches for Test Data Processing
- Elevated Voltage Testing and Stress Testing
- Reliability and Yield
- Nanometer Test Challenges
- Mixed Current/Voltage Testing
- Fault Localization & Diagnosis
- Data-Based Testing
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Advance Program |
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Thursday -- Friday
October 25, 2007 (Thursday) |
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4:00 PM
- 5:10 PM |
Opening Session |
4:00 PM
- 4:10 PM |
Opening Remarks
Hans Manhaeve (Q-Star Test)
M. Tehranipoor (Univ. of Connecticut)
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4:10 PM
- 5:10 PM |
Keynote - Defect-Based Test: What is Our Data Telling Us?
Kenneth M. Butler (Texas Instruments) |
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5:10 PM
- 6:30 PM |
Session 1
Chair - Sreejit Chakrabarty (LSI Logic) |
5:10 PM - 5:40 PM |
Invited Talk - We Are Done with Scan & Memory BIST. Where is DFT Headed Next?
R. Raina (Freescale) |
5:40 PM - 6:10 PM |
Invited Talk - Defect Based Testing / A Diagnostics Perspective
T. Bartenstein (Cadence) |
6:10 PM - 6:30 PM |
High Speed Localization and Visualization of Blocked Chain Defects
J. Orbon & A. Crouch (Inovys) |
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7:00 PM
- 9:00 PM |
Welcome Reception |
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October 26, 2007 (Friday) |
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8:00 AM
- 9:00 AM |
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Keynote - Opportunities with Process Variation
TM Mak (Intel) |
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9:00 AM
- 10:20 AM |
Session 2
Chair - Xiaoqing Wen (Kyushu Institute of Tech.) |
9:00 AM - 9:20 AM |
Dynamic N-Detect Patterns Based on Equivalent Faults
P. Reuter and Y. Huang (Mentor Graphics)
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9:20 AM - 9:35 AM |
Small Delay Defect Detection Using Self-Relative Timing Bounds
R. Helinski, J. Plusquellic (UMBC)
M. Tehranipoor (Univ. of Connecticut) |
9:35 AM - 9:50 AM |
Interconnect Open Detection by Supply Current Testing under AC Electric Field Application
M. Hashizume, Y. Ogata, M. Tojo, M. Ichimiya, H. Yotsuyanagi (Univ. of Tokushima) |
9:50 AM - 10:05 AM |
Temporal Analysis and Spatial Deconvolution of Power Pad Transients Signals for Fault Localization
R. M. Rad and J. Plusquellic (UMBC) |
10:05 AM - 10:20 AM |
Towards an optimal combination of Logic and Current tests in function of product quality and test cost
requirements
H. Manhaeve, S. Kerckenaere (Q-Star Test)
G. Eide (Magma)
J. Brenkuš (Slovak Univ. of Tech.) |
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10:20 AM - 10:40 AM BREAK |
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10:40 AM
- 12:00 PM |
Session 3
Chair – Anuja Sehgal (AMD) |
10:40 AM - 11:00 AM |
Test-Pattern Grading for Small-Delay Defects
M. Yilmaz, K. Chakrabarty (Duke University)
M. Tehranipoor (Univ. of Connecticut) |
11:00 AM - 11:20 AM |
A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set
K. Miyase, X. Wen, S. Kajihara, M. Yamamoto, and H. Furukawa (Kyushu
Institute of Technology) |
11:20 AM - 11:40 AM |
Theoretical and Practical Aspects of IDDQ Measurement Settling
B. Straka, H. Manhaeve, S. Kerckenaere (Q-Star Test)
J. Brenkuš (Slovak Univ. of Tech.)
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11:40 AM - 12:00 PM |
On the Potential of Test Pattern Generation to Improve Current-Based Testing and Diagnosis
Techniques
C. Thibeault (Ecole de technologie supérieure) |
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12:00 PM - 1:00 PM LUNCH |
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1:00 PM
- 2:20 PM |
Session 4
Geir Eide (Magma Design Automation) |
1:00 PM - 1:30 PM |
Invited Talk - Defect-Based Testing with Adaptive Flows
R. Dassch (Portland State University) |
1:30 PM - 2:00 PM |
Invited Talk - Defect & Failure Mode Trends
L. Chadwick and P. Nigh (IBM) |
2:00 PM - 2:20 PM |
A Defect-Tolerant Interconnect Mechanism for Nanoscale Architectures
A. Namazi, M. Nourani and M. Saquib (Univ. of Texas at Dallas) |
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2:20 PM
- 2:40 PM BREAK |
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2:40 PM
- 4:00 PM |
Panel Discussion: Process Variations + Systematic Defects |
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Moderator: Hank Walker (Texas A&M Univ.)
Panelists:
Rob Aitken (ARM)
John Caroulli (Texas Instruments)
Al Crouch (Inovys)
Phil Nigh (IBM) |
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Registration |
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For more information on registration please visit the online registration. |
Additional Information |
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General Information
Hans Manhaeve
General Chair
Q-Star Test
L.Bauwensstraat 20
Bruegge, Belgium
Tel: +32 50 319273. +32 50 312350(FAX)
E-mail: Hans.Manhaeve@qstar.be
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Committees |
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Co-General Chair
Mehdi Tahoori
Northeastern University, USA
Vice General Chair
Sankaran Menon
Intel Corporation, USA
Program Chair
Mohammad Tehranipoor
Univ. of Connecticut, USA
Vice-Program Chair
Jim Plusquellic
Univ. of Maryland, Baltimore County, USA
Finance Chair
Sankaran M. Menon
Intel Corporation, USA
Publicity Chair
Jaume Segura
UIB Baleares, Spain
Advisor
Charles Hawkins
University of New Mexico, USA
Steering Committee
Yashwant K. Malaiya (Chair), Colorado State University, USA
Anura Jayasumana Col State Univ, USA
Joan Figueras, UPC, Barcelona, Spain
Adit Singh, Auburn University, USA
Duncan (Hank) Walker, Texas A&M Univ.
Program Committee
Robert Aitken, ARM, USA
Subhasish Mitra, Stanford Univ., USA
Chintan Patel, UMBC, USA
Jerry Soden, Sandia National Labs, USA
Michel Renovell, LIRMM, France
Krish Chakrabarty, Duke Univ., USA
Claude Thibeault,Ecole de Tech Sup,Canada
Sreejit Chakravarty, LSI Logic, USA
Martin Margala, U-Mass, USA
Sule Ozev, Duke University
Xiaoqing Wen (Kyushu Institute of Technology)
Shawn Blanton, CMU, USA
Anuja Sehgal, AMD
Sagar Sabade, Qualcomm
Nilanjan Mukherjee, Mentor Graphics
Robert Daasch, Portland State Univ.
Rajesh Raina, Freescale, USA
Geir Eide, Magma, USA
Manoj Sachdev, Univ. of Waterloo, Canada
Anne Gattiker, IBM, USA
Tom Bartenstein, Cadence, USA
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IEEE International Workshop On Current & Defect Based Testing is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer
Society's Test Technology Technical Council (TTTC). |